HBM vs. PCIe
Comparing 2 standards across 10 specifications. 10 key differences identified.
HBM (High Bandwidth Memory), standardized by JEDEC in October 2013, takes a fundamentally different approach from GDDR -- stacking multiple DRAM dies vertically and connecting them via through-silicon vias next to the GPU on a silicon interposer, trading GDDR's narrower, faster-clocked bus for a much wider, slower one. Manufacturing cost has kept it mostly in high-end compute GPUs rather than mainstream cards.
PCIe is the interface standard graphics cards connect through, typically using all 16 lanes of a slot for maximum bandwidth. Each generation has roughly doubled per-lane throughput since 2003, from PCIe 1.0's 250 MB/s per lane to PCIe 6.0's 7.56 GB/s per lane using a new PAM4 signaling scheme.
Specification Comparison Table
10 Parameters| Parameter / Spec | ||
|---|---|---|
|
JEDEC Standard
|
October 2013 (JESD235) | — |
|
Architecture
|
Vertically stacked DRAM dies, through-silicon vias (TSVs), silicon interposer | — |
|
Bus Width (4-Hi Stack)
|
1024-bit (8 x 128-bit channels) | — |
|
Typical Use
|
High-end compute/datacenter GPUs, not mainstream consumer cards | — |
|
PCIe 1.0 (2003)
|
— | 0.25 GB/s/lane | 4 GB/s x16 |
|
PCIe 2.0 (2007)
|
— | 0.5 GB/s/lane | 8 GB/s x16 |
|
PCIe 3.0 (2010)
|
— | 0.985 GB/s/lane | 15.75 GB/s x16 |
|
PCIe 4.0 (2017)
|
— | 1.969 GB/s/lane | 31.51 GB/s x16 |
|
PCIe 5.0 (2019)
|
— | 3.938 GB/s/lane | 63.02 GB/s x16 |
|
PCIe 6.0 (2022 spec)
|
— | 7.563 GB/s/lane | 121 GB/s x16 |