HBM vs. HBM3
Comparing 2 standards across 7 specifications. 7 key differences identified.
HBM (High Bandwidth Memory), standardized by JEDEC in October 2013, takes a fundamentally different approach from GDDR -- stacking multiple DRAM dies vertically and connecting them via through-silicon vias next to the GPU on a silicon interposer, trading GDDR's narrower, faster-clocked bus for a much wider, slower one. Manufacturing cost has kept it mostly in high-end compute GPUs rather than mainstream cards.
HBM3, announced by JEDEC in January 2022, doubled channel count to 16 within the same 1024-bit bus width and reaches roughly 819 GB/s of bandwidth per stack. It's used predominantly in AI and datacenter accelerators like Nvidia's H100, rather than consumer graphics cards.
Specification Comparison Table
7 Parameters| Parameter / Spec | ||
|---|---|---|
|
JEDEC Standard
|
October 2013 (JESD235) | January 2022 |
|
Architecture
|
Vertically stacked DRAM dies, through-silicon vias (TSVs), silicon interposer | — |
|
Bus Width (4-Hi Stack)
|
1024-bit (8 x 128-bit channels) | — |
|
Typical Use
|
High-end compute/datacenter GPUs, not mainstream consumer cards | — |
|
Channels
|
— | 16 x 64-bit (1024-bit total bus, same as HBM2) |
|
Max Bandwidth / Data Rate
|
— | ~819 GB/s per stack |
|
Primary Use
|
— | AI/datacenter accelerators |