HBM2 vs. PCIe
Comparing 2 standards across 10 specifications. 10 key differences identified.
HBM2, standardized by JEDEC in January 2016, doubled HBM's maximum stack height to 8 dies and its per-pin transfer rate, reaching up to 256 GB/s of bandwidth per stack and 8GB of capacity per package.
PCIe is the interface standard graphics cards connect through, typically using all 16 lanes of a slot for maximum bandwidth. Each generation has roughly doubled per-lane throughput since 2003, from PCIe 1.0's 250 MB/s per lane to PCIe 6.0's 7.56 GB/s per lane using a new PAM4 signaling scheme.
Specification Comparison Table
10 Parameters| Parameter / Spec | ||
|---|---|---|
|
JEDEC Standard
|
January 2016 (JESD235a) | — |
|
Max Dies Per Stack
|
8 | — |
|
Max Bandwidth / Data Rate
|
256 GB/s per stack | — |
|
Available Capacity Range
|
8GB per package | — |
|
PCIe 1.0 (2003)
|
— | 0.25 GB/s/lane | 4 GB/s x16 |
|
PCIe 2.0 (2007)
|
— | 0.5 GB/s/lane | 8 GB/s x16 |
|
PCIe 3.0 (2010)
|
— | 0.985 GB/s/lane | 15.75 GB/s x16 |
|
PCIe 4.0 (2017)
|
— | 1.969 GB/s/lane | 31.51 GB/s x16 |
|
PCIe 5.0 (2019)
|
— | 3.938 GB/s/lane | 63.02 GB/s x16 |
|
PCIe 6.0 (2022 spec)
|
— | 7.563 GB/s/lane | 121 GB/s x16 |