HBM3 vs. PCIe
Comparing 2 standards across 10 specifications. 10 key differences identified.
HBM3, announced by JEDEC in January 2022, doubled channel count to 16 within the same 1024-bit bus width and reaches roughly 819 GB/s of bandwidth per stack. It's used predominantly in AI and datacenter accelerators like Nvidia's H100, rather than consumer graphics cards.
PCIe is the interface standard graphics cards connect through, typically using all 16 lanes of a slot for maximum bandwidth. Each generation has roughly doubled per-lane throughput since 2003, from PCIe 1.0's 250 MB/s per lane to PCIe 6.0's 7.56 GB/s per lane using a new PAM4 signaling scheme.
Specification Comparison Table
10 Parameters| Parameter / Spec | ||
|---|---|---|
|
JEDEC Standard
|
January 2022 | — |
|
Channels
|
16 x 64-bit (1024-bit total bus, same as HBM2) | — |
|
Max Bandwidth / Data Rate
|
~819 GB/s per stack | — |
|
Primary Use
|
AI/datacenter accelerators | — |
|
PCIe 1.0 (2003)
|
— | 0.25 GB/s/lane | 4 GB/s x16 |
|
PCIe 2.0 (2007)
|
— | 0.5 GB/s/lane | 8 GB/s x16 |
|
PCIe 3.0 (2010)
|
— | 0.985 GB/s/lane | 15.75 GB/s x16 |
|
PCIe 4.0 (2017)
|
— | 1.969 GB/s/lane | 31.51 GB/s x16 |
|
PCIe 5.0 (2019)
|
— | 3.938 GB/s/lane | 63.02 GB/s x16 |
|
PCIe 6.0 (2022 spec)
|
— | 7.563 GB/s/lane | 121 GB/s x16 |